This invention relates to electrical interconnection of integrated circuit chips and, particularly, to interconnection of assemblies including one or more integrated circuit chips.
A typical semiconductor die has a front (“active”) side, in which the integrated circuitry is formed, a back side, and sidewalls. The sidewalls meet the front side at front edges and the back side at back edges. Semiconductor die typically are provided with interconnect pads (die pads) located at the front side for electrical interconnection of the circuitry on the die with other circuitry in the device in which the die is deployed. Some die as provided have die pads on the front side along one or more of the die margins, and these may be referred to as peripheral pad die. Other die as provided have die pads arranged in one or two rows at the front side near the center of the die, and these may be referred to as central pad die. The die may be “rerouted” to provide a suitable arrangement of interconnect pads at or near one or more of the margins of the die. A die margin along which interconnect pads are arranged may be referred to as an “interconnect margin”, the adjacent front die edge may be referred to as an “interconnect edge”, and a die sidewall adjacent an interconnect die edge may be referred to as an “interconnect sidewall”.
Semiconductor die may be electrically connected with other circuitry, for example in a printed circuit board, a package substrate or leadframe, or another die, by any of several means. Connection may be made, for example, by wire bonds, or by flip chip interconnects, or by tab interconnects.
T. Caskey et al. U.S. application Ser. No. 12/124,097, filed Mar. 12, 2009, titled “Electrical interconnect formed by pulse dispense”, which is incorporated herein by reference, describes electrical interconnection of die by depositing a curable electrically conductive material over the features to be connected and curing the material to form electrically conductive traces. Suitable curable materials include conductive polymers or conductive inks, for example.
A dielectric coating formed over the die surface prior to forming the interconnects surface serves to insulate features that might otherwise be contacted by the electrically conductive traces, but to which electrical contact is not desired, such as the die margins along which the die pads are situated, and the adjacent die edges and sidewalls; and die pads over which the traces may pass, but which are not intended to be electrically connected to other features. The dielectric coating may by any of a variety of materials, and may be formed using any of a variety of techniques as appropriate for the particular material. Suitable materials include organic polymers, and particularly suitable materials include parylenes, which are formed by in situ polymerization of precursor molecules in vapor form. The coating covers all surfaces that are exposed to the material during the coating process, including areas where electrical connection is to be made. Accordingly, openings are formed over selected areas where contact with the conductive traces is desired, for example by selective laser ablation.
A number of approaches have been proposed for increasing the density of active semiconductor circuitry in integrated circuit chip packages, while minimizing package size (package footprint, package thickness). In one approach to making a high density package having a smaller footprint, two or more semiconductor die, of the same or different functionality, are stacked one over another and mounted on a package substrate.
S. J. S. McElrea et al. U.S. application Ser. No. 12/124,077, filed May 20, 2008, titled “Electrically interconnected stacked die assemblies”, which is incorporated herein by reference, describes stacked die assemblies having various stacking configurations in which electrical interconnection is made using an interconnect material such as a material that includes a conductive polymer or a conductive ink, for example. In some configurations, for example (among others), each die has interconnect pads situated in a margin along an interconnect edge, and succeeding die in the stack arranged so that their respective interconnect edges face toward the same face of the stack, and the interconnect die edges are offset so that the configuration presents as a stairstep die stack, and the interconnections are made over the steps.
At reduced pad pitch, adjacent traces are close together and, depending on the particular interconnect material and the particular underlying dielectric coating, the interconnect material may “bleed” laterally, so that the edges of adjacent traces meet or overlap, causing electrical leakage between the adjacent traces. Such electrical leakage is not acceptable.